Speaking at DVClub Austin September 2023

I’m looking forward to speaking at DVClub this Thursday. If you are in Austin you can register for free below.

The topic of my talk will be a paper I presented at DVCon 2021 “Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods”. If you haven’t been to a DVClub event before, you will enjoy it! There is typically a catered lunch and one or two guest speakers. The talks are of general interest and typically touch verification, but sometimes industry topics.

There is a strong emphasis that the talks are more academic and not a push for tools; in full disclosure, I do work at an EDA tool company today, but this talk is a technique that is universal and looks at possible connections between formal and synthesis. I like the topic and hope you will be able to come!

If you wanted to check out the paper of the slides they are linked below.

• Paper

• Slides

DVClub Austin, September 28, 2023
11:30 am - 1:30pm
Norris Conference Center
Register

Better Web Conferencing

On Nov 12th I gave a talk to the IEEE Twin Cities Consulting Network on “Better Video Conferencing” with my thoughts and gear I use for video conferencing. Below are the slides. The talk was stories and background on the choices I made in putting together the setup.

Thanks for letting me present!

Slides in PDF Format.

Owning a Tesla Going Electric Update

On 10/26/2020 I gave a short update to a presentation I made in March 2019 on the same topic. Followed by a question and answer for the IEEE Coulee Subsection with the slides (PDF) below.

Slides

The 2019 IEEE and MFESTS Engineering Week Banquet in the Twin Cities

The IEEE Twin Cities Section and MFESTS (Minnesota Federation of Engineering, Science and Technology Societies) is having their annual banquet this Saturday, Feb 23rd in St. Paul at 5:30 pm. You should come!

Imagine saying to your significant other tonight:

“I want to dress up like a suave gentleman / sophisticated lady and bring you to an event at the beautiful James B. Woulfe Alumni Hall on the St. Thomas Campus. Where we will eat a first class meal while listening to a local keynote speaker and entrepreneur Phil Magney speak on the topic of autonomous cars. We’ll witness Minnesota engineers and scientists getting honored for their work with awards such as the prestigious MFESTS Distinguished Engineer. We’d be surrounded by the best and brightest in Minnesota from all the engineering disciplines who keep our local economy strong - what a great place to meet people doing good on so many levels! And … I hear there will be flying shark and fish dirigibles we can play with!”

I’m serving as the IEEE Twin Cities Section Chair for 2019. I'll be the co-master-of-ceremonies of the event for the second time this year. I’ve been to a number of these joint Engineering Week Banquets. From learning about US Bank Stadium last year from John Farstad CTO of US Bank Stadium. To Prof. Paul Imbertson from the UMN delivering a keynote a few years ago talking about mentorship and legacy that really touched me. There are few places where engineers meet, and even fewer where distinguished engineers from different engineering disciplines meet. An event like this is a great place to be a part of the engineering community.

This is a great event and you should go. Tickets are on sale now and we want to sell the event out! We are getting so close.

Purchase your tickets here by clicking on “External Registration” to get them through eventbrite.

See you there!

James B. Woulfe Alumni Hall on the St. Thomas Campus

Owning a Tesla: Going Electric Talk at IEEE Rochester, Minnesota

I had given a talk in September, 2018 titled “Owning a Tesla: Going Electric” for the IEEE Twin Cities Section on my experiences as a Tesla owner with my Model S.

I’m excited to share that I will be giving an updated version of that talk tomorrow, Monday, January 28th 2019, in Rochester, Minnesota for the IEEE Southern Minnesota Section.

The event is free and open to the public. There may even be free pizza ;)

The details and signup for the event are available here - please RSVP to help with planning. Talk at 6:30 pm on Monday, January 28th, 2019.

I’ll be talking on topics below:

• Cost per Mile versus a traditional ICE (internal combustion engine)

• Projected Maintence and Costs

• Engineering tricks that make the Tesla suite of vehicles capable of over 300 miles range

• How the Tesla Supercharger Network Works

• Teslas in recent Extreme Cold

• and more

The slides I used are available here in PDF format.

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Blog

Humble Book Bundle of O'Reilly Books - Head First Design Patterns

A few years ago I wrote a paper for the Design and Verification Conference inspired by the book “Head First Design Patterns” by Robson and Freeman. “Head First Design Patterns” is an excellent way to learn about Design Patterns. I liked the style of the book, which was lighthearted and written in a conversational tone. It made learning about Design Patterns actually fun!

I have a paper copy, of course, of the book. But, I saw that Humble Bundle had a “Head First Series by O’Reilly” bundle sale for the next week which includes “Head First Design Patterns” in ebook and PDF formats.

If you are looking for a cost effective way of getting “Head First Design Patterns” and other O’Reilly Head First Books this is a great way to get them. This is not an affiliate link and I get no kick back, but I wanted to share it with you since I loved the book. A large and configurable portion of the proceeds go to charity when using this Humble Bundle. The charity in this case is Code for America, a non-profit.

In order to get “Head First Design Patterns” you would need to buy it at the $15 or above level. I just bought it myself and am happy to now have an electronic copy of this book! The bundle ends on Oct 14, 2018.

Humble Book Bundle: Head First Series by O’Reilly
https://www.humblebundle.com/books/head-first-books

Ten Thousand Failures Now with SSL

I saw that my hosting provider now supports SSL which is a nice upgrade. As a visitor you get encrypted and possibly faster response time since it uses HTTP2 style communication too.

Implicit Port Connections Summary

I was working on a testbench and made a mistake. I saw a SystemVerilog code construct I wasn't used to and "corrected" it. I ended up disconnecting a port that was implicitly connected. There is already an authorative paper on this subject "SystemVerilog Implicit Port Connections by Cliff Cummings" which is very good.

I'd like to share a one page example that shows the differences. In the code posted on Github here I create a simple dut that uses the two different ways of using SystemVerilog implicit port connection. The one I made the mistake on was called ".name implicit port connections".

mul ex3 (.mult, .mop1, .data);
mul ex1 (.mult, .mop1, .data());

The two lines above are very different. The top line will use the .name implict port connection to connect all three ports. The second line will use the .name implicit port connection to connect only two ports and explicitly leave floating the .data port.

The example code when seen as a schematic in Mentor Visualizer is below. We can see that instance ex3 and ex4 get connected to the "data" input port. But ex1 and ex2 do not - because we are not allowing the implicit port connections to happen for two different reasons.

uvm_report_object Feature Examples

UVM has a powerful display capability baked into it from the uvm_report_object. Using it allows for capabilities such as:

• getting the debug info you want out of components without being blinded by everything
• silencing messages you don't want to see
• breaking out detailed logs into seperate files to not clutter up the simulation logs for everyone else

I put together a reference environment on GitHub that goes through exercises using the uvm_report_object here. Included is also the text output of the simulaton so you can print the code as well as the output and follow along.

SystemVerilog Constraint Layering Examples from John Dickol

DVCon 2015 had a paper by John Dickol titled "SystemVerilog Constraint Layering via Reusable Randomization Policy Classes" that described how SystemVerilog constraints could be layered onto an object. The previous method was to do a factory override or extend the class to get this type of behavior.

I loved the idea. It solves a lot of problems such as having to create and manage extended classes who only exist to further constrain an object. Plus you get the ability to recombine constraints during the sim - which is amazing. In order to make sure I understood his approach and to do the examples myself, I have written out the complete code from his paper. I have made this code available with the author's permission on my Github account here.

The code in the paper builds upon itself with each additive iteration. This means that classes are getting overwritten with new versions of itself and sometimes classes go away as the paper moves on. If you would like to follow along with his paper it might be helpful to have the full source code for each Figure available to experiment with or to reference in the future. The paper sometimes groups many figures into one example. The list below shows what figure from the Dickol paper is represented in which folder. Each folder has a Mentor Questa .do file that can launch the simulation and then print out five example randomizations.

I added a few non-referenced items to the code that are not explicitly described in the paper like: class addr_range and type addr_t. And added a testbench to try out the code examples, but all of the ideas are credited to John Dickol and his excellent paper!

Folder and Figures from paper:

• A
  • Figure 1
  • Figure 2
  • Figure 3
• B
  • Figure 4
• C
  • Figure 5
• D
  • Figure 6
• E
  • Figure 7
  • Figure 8
• F
  • Figure 9
  • Figure 10
• G
  • Figure 11

Example Command to Simulate with Mentor Questa

cd A
vsim -c -do compile.do

DVCon 2015 Paper and Presentation

I have a paper and a presentation session slot at DVCon 2015 (Design and Verification Conference) in San Jose, California. The title of the paper is "Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches" and I am excited to share it with the verification community.

It will be presented on Wednesday, March 4th in the Monterey/Carmel hall in the afternoon Coverage sessions.

My Session Number is 13.3 for more information click here.

If you are attending the conference and liked my presentation / paper please vote at www.dvcon.org/2015/vote.

The paper and the slides used in the presentation are now available at this link on the DVCon website.