Improving Constrained Random Testing - Second Place Paper at DVCon 2017

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

The actual paper, slides and GitHub repo links are below:

The inspiration for the paper is from Tom Murphy VII who in this YouTube video introduces his research on an AI for playing Nintendo games. I take ideas presented by Murphy VII and apply the presented principles to the Verification realm and got interesting and possibly promising results. I recommend checking out Murphy's YouTube channel and his follow up videos he has on the topic - all of which are very funny and brilliant!

My paper was awarded second place in the DVCon 2017 paper competition. I'd like to thank my peers who took the time to vote! I give due credit to the talented Stan Sokorac of ARM who won best paper; who also presented in the same session as me. I had a great time presenting at DVCon this year. I hope to return to DVCon next year!