Verification
Eldon Nelson
Improving Constrained Random Testing - Second ...

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

Improving Constrained Random Testing - Second Place Paper at DVCon 2017
Verification
Eldon Nelson
Best Paper at Design and Verification ...

I'm honored to share that my paper:

"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"

was awarded Best Paper at the Design and Verification Conference (DVCon) 2016.  The link to the final paper is now available.

Best Paper at Design and Verification Conference 2016
Verification
Eldon Nelson
One Parameterized Bind to Bind Them All

The SystemVerilog bind command allows for adding new functionality to a module.  Typically, it is used to add new checking to a RTL block.

I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used.  When you think about what bind is actually doing it starts to make sense.

One Parameterized Bind to Bind Them All
Verification
Eldon Nelson
Implicit Port Connections Summary
Implicit Port Connections Summary
Verification
Eldon Nelson
uvm_report_object Feature Examples
uvm_report_object Feature Examples

FT2232H

FTDI FT2232 MPSSE Basics

FTDI FT2232 MPSSE Basics

I started a project working on interfacing with the Future Technology Devices International Ltd. (FTDI) USB FT2232H Mini Module via their D2XX device driver.  This device hooks up to a computer through a standard USB port and has a series of pins that can be used to interface with JTAG, I2C, and whatever serial like protocol you want.  I had been using the Application Note AN_135 FTDI MPSSE Basics provided by the manufacturer and noticed that their Example Program (Chapter 5), which is very good, was not available for download, but only printed in pieces in their Application Note.  As I went through the Application Note, I was writing out the example along with their comments and had a few minor corrections to get it working in a Linux environment.

I am making my transcription of the Example Program and corrections available on GitHub below.