Verification
Eldon Nelson
Improving Constrained Random Testing - Second ...

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

Improving Constrained Random Testing - Second Place Paper at DVCon 2017
Verification
Eldon Nelson
Best Paper at Design and Verification ...

I'm honored to share that my paper:

"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"

was awarded Best Paper at the Design and Verification Conference (DVCon) 2016.  The link to the final paper is now available.

Best Paper at Design and Verification Conference 2016
Verification
Eldon Nelson
One Parameterized Bind to Bind Them All

The SystemVerilog bind command allows for adding new functionality to a module.  Typically, it is used to add new checking to a RTL block.

I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used.  When you think about what bind is actually doing it starts to make sense.

One Parameterized Bind to Bind Them All
Verification
Eldon Nelson
Implicit Port Connections Summary
Implicit Port Connections Summary
Verification
Eldon Nelson
uvm_report_object Feature Examples
uvm_report_object Feature Examples

SystemVerilog

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Speaking at DVClub Austin September 2023

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I’m looking forward to speaking at DVClub this Thursday. If you are in Austin you can register for free below.

The topic of my talk will be a paper I presented at DVCon 2021 “Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods”. If you haven’t been to a DVClub event before, you will enjoy it! There is typically a catered lunch and one or two guest speakers. The talks are of general interest and typically touch verification, but sometimes industry topics.

There is a strong emphasis that the talks are more academic and not a push for tools; in full disclosure, I do work at an EDA tool company today, but this talk is a technique that is universal and looks at possible connections between formal and synthesis. I like the topic and hope you will be able to come!

If you wanted to check out the paper of the slides they are linked below.

DVClub Austin, September 28, 2023
11:30 am - 1:30pm
Norris Conference Center
Register

Improving Constrained Random Testing - Second Place Paper at DVCon 2017

Improving Constrained Random Testing - Second Place Paper at DVCon 2017

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

One Parameterized Bind to Bind Them All

One Parameterized Bind to Bind Them All

The SystemVerilog bind command allows for adding new functionality to a module.  Typically, it is used to add new checking to a RTL block.

I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used.  When you think about what bind is actually doing it starts to make sense.

SystemVerilog Constraint Layering Examples from John Dickol

DVCon 2015 had a paper by John Dickol titled "SystemVerilog Constraint Layering via Reusable Randomization Policy Classes" that described how SystemVerilog constraints could be layered onto an object. The previous method was to do a factory override or extend the class to get this type of behavior.

I loved the idea. It solves a lot of problems such as having to create and manage extended classes who only exist to further constrain an object. Plus you get the ability to recombine constraints during the sim - which is amazing. In order to make sure I understood his approach and to do the examples myself, I have written out the complete code from his paper. I have made this code available with the author's permission on my Github account here.

The code in the paper builds upon itself with each additive iteration. This means that classes are getting overwritten with new versions of itself and sometimes classes go away as the paper moves on. If you would like to follow along with his paper it might be helpful to have the full source code for each Figure available to experiment with or to reference in the future. The paper sometimes groups many figures into one example. The list below shows what figure from the Dickol paper is represented in which folder. Each folder has a Mentor Questa .do file that can launch the simulation and then print out five example randomizations.

I added a few non-referenced items to the code that are not explicitly described in the paper like: class addr_range and type addr_t. And added a testbench to try out the code examples, but all of the ideas are credited to John Dickol and his excellent paper!

Folder and Figures from paper:

  • A
    • Figure 1
    • Figure 2
    • Figure 3
  • B
    • Figure 4
  • C
    • Figure 5
  • D
    • Figure 6
  • E
    • Figure 7
    • Figure 8
  • F
    • Figure 9
    • Figure 10
  • G
    • Figure 11

Example Command to Simulate with Mentor Questa

cd A
vsim -c -do compile.do

Verilog Flip-Flop Macros by Chris Drake

Verilog Flip-Flop Macros by Chris Drake

Chris Drake's blog Fuzzy Logic had a particular post titled Verilog Flip-Flop Macros which I thought was really good. It deals with creating an abstraction of a flip-flop in SystemVerilog.  I had to try out his example code myself to verify the performance differences he experienced.

The Strategy Pattern in SystemVerilog

The Strategy Pattern in SystemVerilog

I had watched a wonderful video series of Object Oriented Design Patterns on Lynda.com called "Foundations of Programming: Design Patterns" by Elisabeth Robinson and Eric Freeman.  In their series, they go through some of the ideas in "Design Patterns" and have very concise code examples that illustrate specific Design Patterns.

I highly recommend checking out "Foundations of Programming: Design Patterns" and checking out Lynda.com - if you haven't heard of them before.

The example code from the video series is, of course, not written in SystemVerilog.  It is written in Java.  From the Lynda.com site you can download for free the Java example code.  As an interested student, I took their example code and rewrote it in SystemVerilog, staying as close as possible to the original and published the result on GitHub below.

Merging SystemVerilog Covergroups by Example Article in Mentor's Verification Horizons

Merging SystemVerilog Covergroups by Example Article in Mentor's Verification Horizons

There were two early articles on this blog that I wrote dealing with merging SystemVerilog covergroups:

The two posts were rewritten and are now available in Mentor's "Verification Horizons" June 2014 quarterly publication under the title "Merging SystemVerilog Covergroups by Example".  I'm happy with how it turned out.

Display Monitor and Strobe in SystemVerilog

Display Monitor and Strobe in SystemVerilog

I was adding in the ubiquitous "what is this code doing" debug statements to some SystemVerilog to trace what was happening and finally had a chance to consider deeply the application of: $monitor, $display and $strobe.  All three print to the display and all use the same syntax and formatting in their arguments.  The difference in the three is when they actually execute.  I read a pretty good starting article Verilog subtleties – $monitor vs. $display vs. $strobe that gave me a start to creating my own teaching version of their example.

You can check out the code below on github.

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Using Squarespace and Embedding Syntax Highlighted Code with Emacs

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Using Squarespace and Embedding Syntax Highlighted Code with Emacs

Squarespace has the ability to syntax highlight the following three source types:

  • html
  • css
  • javascript

in a very workable built in code block in their blogging system.  But, if you use another source type like SystemVerilog or Python you will have to figure out something else to get your source code syntax highlighted on Squarespace.

In the following post on Answers Squarespace, it mentions a method using the javascript helper Prism that can syntax highlight a lot of languages out of the box.  It actually looks really cool.  Sadly, SystemVerilog is not in their list of supported languages.

To handle something like SystemVerilog, or nearly every language, the solution I ended up with was using Emacs with the plugin htmlize.  The idea is that since Emacs already has great syntax highlighting for everything, you can export regions or whole files to raw HTML with that syntax highlighting intact.

Mentor Questa do versus source

Mentor Questa do versus source

The standard TCL command "source" is the common way to read in source of one file into the current environment - similar to an `include in Verilog.  Mentor Questa runs a TCL interpreter and adds a few custom features to the environment one of which is the command: "do".  For many uses the "do" and the "source" command will have identical output.  In fact, whatever can be done with "source" can be done with "do" - it is a superset of "source".  The "do" command does add at least two useful or at least interesting features.

SystemVerilog timescale Across Classes Illustrated

SystemVerilog timescale Across Classes Illustrated

Mixing of `timescale(s) causes problems if you are trying to pass delays as realtime types.  The realtime type was never meant to be treated this way.  realtime is actually a standard real type but with only local knowledge of the meaning of the units of time.  When you pass a realtime value into a class in a different package all you get is that real type value and no units.

SystemVerilog Package Globals instead of `include

SystemVerilog Package Globals instead of `include

I had used other programming languages before working with System Verilog.  So when I started looking at System Verilog code for the first time, I was perplexed why there were all of these `includes all over - even in purely object oriented verification logic.

There is a problem and proposed solution I would like to share.  Using packages instead of `include to store constants.  I wrote the example both ways: package and `include; so you can see something that I see typically done with `include done with packages.  

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Using Emacs to Debug Verilog Compiles in Mentor Questa

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Using Emacs to Debug Verilog Compiles in Mentor Questa

I hadn't used Emacs to compile and parse errors for Mentor Questa before and decided to see what that would be like.  Making Emacs understand how the simulator works and spits out errors involves extending Emacs to know how to launch your Verilog simulator and how to interpret the console messages.  The built in Emacs compilation mode is not terrible and at least gives a starting point for compiling and debugging standard languages and custom ones. This is how to do it with Mentor Questa.

Merging SystemVerilog Covergroups for Efficiency

Merging SystemVerilog Covergroups for Efficiency

In the previous blog post, we were merging covergroups and, in all cases, keeping track of the covergroup instances "INST" (the Mentor Questa notation) data as well.  This is perfectly fine if you have only a few repeated instances. But, what if you have thousands of instances in your design - the covergroup data can get bloated.