DVCon 2015 Paper and Presentation

I have a paper and a presentation session slot at DVCon 2015 (Design and Verification Conference) in San Jose, California. The title of the paper is "Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches" and I am excited to share it with the verification community.

It will be presented on Wednesday, March 4th in the Monterey/Carmel hall in the afternoon Coverage sessions.

My Session Number is 13.3 for more information click here.

If you are attending the conference and liked my presentation / paper please vote at

The paper and the slides used in the presentation are now available at this link on the DVCon website.

Merging SystemVerilog Covergroups for Efficiency

Merging SystemVerilog Covergroups for Efficiency

In the previous blog post, we were merging covergroups and, in all cases, keeping track of the covergroup instances "INST" (the Mentor Questa notation) data as well.  This is perfectly fine if you have only a few repeated instances. But, what if you have thousands of instances in your design - the covergroup data can get bloated.