I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:
"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"
Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.
I'm honored to share that my paper:
"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"
was awarded Best Paper at the Design and Verification Conference (DVCon) 2016. The link to the final paper is now available.
The SystemVerilog bind command allows for adding new functionality to a module. Typically, it is used to add new checking to a RTL block.
I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used. When you think about what bind is actually doing it starts to make sense.
I was trying to get a metric for the performance penalty of simulating with and without a model parameter. The parameter was believed to be responsible for a performance difference of 10% to 15%, but after looking at the data more I became intrigued. Since no one had really deep dived into this and shown more than a few data points on performance it was time to get serious about simulation performance comparisons.
I started a project working on interfacing with the Future Technology Devices International Ltd. (FTDI) USB FT2232H Mini Module via their D2XX device driver. This device hooks up to a computer through a standard USB port and has a series of pins that can be used to interface with JTAG, I2C, and whatever serial like protocol you want. I had been using the Application Note AN_135 FTDI MPSSE Basics provided by the manufacturer and noticed that their Example Program (Chapter 5), which is very good, was not available for download, but only printed in pieces in their Application Note. As I went through the Application Note, I was writing out the example along with their comments and had a few minor corrections to get it working in a Linux environment.
I am making my transcription of the Example Program and corrections available on GitHub below.
Your FlexLM License server might be behind a firewall that makes it unaccessible even if you are VPNed into that network. The FlexLM server could be only listening to machines on a certain subnet of addresses or have some other reason to communicate with only certain machines. That firewall makes things like my post Installing Mentor Questa on Ubuntu much more difficult to complete if you wanted to run something like Mentor Questa on your remote machine.
This is my recipe that will allow you to do the necessary ssh forwarding to be able to communicate with a FlexLM server as if you were at a machine on its native network.
I use Mentor Questa a lot and when I am at work the visual lag of interacting with the GUI is almost imperceptible. But, when I am working remotely that visual lag is, of course, more noticeable. One possible solution that reduces the lag considerably compared to VNC, NX, or Windows Remote Desktop is to run Questa natively on your local computer.
The first problem you will run into is that Questa is only officially supported on Redhat and SUSE Linux. (It is also supported on Microsoft Windows too, but who really does serious engineering work on Windows?) So, if Questa is only supported on two commercial Linux variants are we stuck on installing Redhat at home from the corporate install? Fortunately, no.
You can install Mentor Questa on Ubuntu Linux. I'll go through installing it on Ubuntu 12.04.3 64bit.
I hadn't used Emacs to compile and parse errors for Mentor Questa before and decided to see what that would be like. Making Emacs understand how the simulator works and spits out errors involves extending Emacs to know how to launch your Verilog simulator and how to interpret the console messages. The built in Emacs compilation mode is not terrible and at least gives a starting point for compiling and debugging standard languages and custom ones. This is how to do it with Mentor Questa.
In the previous blog post, we were merging covergroups and, in all cases, keeping track of the covergroup instances "INST" (the Mentor Questa notation) data as well. This is perfectly fine if you have only a few repeated instances. But, what if you have thousands of instances in your design - the covergroup data can get bloated.
