Verification
Eldon Nelson
Improving Constrained Random Testing - Second ...

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

Improving Constrained Random Testing - Second Place Paper at DVCon 2017
Verification
Eldon Nelson
Best Paper at Design and Verification ...

I'm honored to share that my paper:

"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"

was awarded Best Paper at the Design and Verification Conference (DVCon) 2016.  The link to the final paper is now available.

Best Paper at Design and Verification Conference 2016
Verification
Eldon Nelson
One Parameterized Bind to Bind Them All

The SystemVerilog bind command allows for adding new functionality to a module.  Typically, it is used to add new checking to a RTL block.

I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used.  When you think about what bind is actually doing it starts to make sense.

One Parameterized Bind to Bind Them All
Verification
Eldon Nelson
Implicit Port Connections Summary
Implicit Port Connections Summary
Verification
Eldon Nelson
uvm_report_object Feature Examples
uvm_report_object Feature Examples

UVM

Improving Constrained Random Testing - Second Place Paper at DVCon 2017

Improving Constrained Random Testing - Second Place Paper at DVCon 2017

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

uvm_report_object Feature Examples

UVM has a powerful display capability baked into it from the uvm_report_object. Using it allows for capabilities such as:

  • getting the debug info you want out of components without being blinded by everything
  • silencing messages you don't want to see
  • breaking out detailed logs into seperate files to not clutter up the simulation logs for everyone else

I put together a reference environment on GitHub that goes through exercises using the uvm_report_object here. Included is also the text output of the simulaton so you can print the code as well as the output and follow along.