Verification
Eldon Nelson
Improving Constrained Random Testing - Second ...

I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:

"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Abstract
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

Improving Constrained Random Testing - Second Place Paper at DVCon 2017
Verification
Eldon Nelson
Best Paper at Design and Verification ...

I'm honored to share that my paper:

"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"

was awarded Best Paper at the Design and Verification Conference (DVCon) 2016.  The link to the final paper is now available.

Best Paper at Design and Verification Conference 2016
Verification
Eldon Nelson
One Parameterized Bind to Bind Them All

The SystemVerilog bind command allows for adding new functionality to a module.  Typically, it is used to add new checking to a RTL block.

I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used.  When you think about what bind is actually doing it starts to make sense.

One Parameterized Bind to Bind Them All
Verification
Eldon Nelson
Implicit Port Connections Summary
Implicit Port Connections Summary
Verification
Eldon Nelson
uvm_report_object Feature Examples
uvm_report_object Feature Examples

Emacs

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Using Squarespace and Embedding Syntax Highlighted Code with Emacs

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Using Squarespace and Embedding Syntax Highlighted Code with Emacs

Squarespace has the ability to syntax highlight the following three source types:

  • html
  • css
  • javascript

in a very workable built in code block in their blogging system.  But, if you use another source type like SystemVerilog or Python you will have to figure out something else to get your source code syntax highlighted on Squarespace.

In the following post on Answers Squarespace, it mentions a method using the javascript helper Prism that can syntax highlight a lot of languages out of the box.  It actually looks really cool.  Sadly, SystemVerilog is not in their list of supported languages.

To handle something like SystemVerilog, or nearly every language, the solution I ended up with was using Emacs with the plugin htmlize.  The idea is that since Emacs already has great syntax highlighting for everything, you can export regions or whole files to raw HTML with that syntax highlighting intact.

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Using Emacs to Debug Verilog Compiles in Mentor Questa

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Using Emacs to Debug Verilog Compiles in Mentor Questa

I hadn't used Emacs to compile and parse errors for Mentor Questa before and decided to see what that would be like.  Making Emacs understand how the simulator works and spits out errors involves extending Emacs to know how to launch your Verilog simulator and how to interpret the console messages.  The built in Emacs compilation mode is not terrible and at least gives a starting point for compiling and debugging standard languages and custom ones. This is how to do it with Mentor Questa.