I was adding in the ubiquitous "what is this code doing" debug statements to some SystemVerilog to trace what was happening and finally had a chance to consider deeply the application of: $monitor, $display and $strobe.  All three print to the display and all use the same syntax and formatting in their arguments.  The difference in the three is when they actually execute.  I read a pretty good starting article Verilog subtleties – $monitor vs. $display vs. $strobe that gave me a start to creating my own teaching version of their example.

You can check out the code below on github.

The standard TCL command "source" is the common way to read in source of one file into the current environment - similar to an `include in Verilog.  Mentor Questa runs a TCL interpreter and adds a few custom features to the environment one of which is the command: "do".  For many uses the "do" and the "source" command will have identical output.  In fact, whatever can be done with "source" can be done with "do" - it is a superset of "source".  The "do" command does add at least two useful or at least interesting features.

I had used other programming languages before working with System Verilog.  So when I started looking at System Verilog code for the first time, I was perplexed why there were all of these `includes all over - even in purely object oriented verification logic.

There is a problem and proposed solution I would like to share.  Using packages instead of `include to store constants.  I wrote the example both ways: package and `include; so you can see something that I see typically done with `include done with packages.